NAND Designer / Layout
Core
Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
Role type
Senior IC NAND Designer / Layout
Builds
Custom test circuits for NAND flash memory products
Domain
Semiconductor / Memory / Analog & Mixed-Signal Design
Required skills
Transistor-level circuit design, Analog circuit design, Mixed-signal design, CMOS device operation, Layout-dependent effects analysis, XA simulation, Verilog, Python scripting, AI-assisted engineering workflows
Preferred skills
NAND flash memory architecture, Wafer/package level testing, Oscilloscope usage, Logic analyzer usage
Technologies
XA, Verilog, Python, AI tools
Responsibilities
Define circuit functionality and validation criteria based on product specs; Create and optimize schematics and device sizing; Validate circuits using simulation and mixed-signal environments; Collaborate with layout teams on parasitics and guard rings; Evaluate risks like leakage and EM/IR; Create test sequences for wafer and package levels; Debug first-silicon and correlate simulation with silicon data; Develop automation scripts and AI solutions for design efficiency; Document design decisions and technical recommendations.
Seniority
Mid-Senior, hands-on IC
