Staff ESD/Latch-up Engineer, HBM Design Architecture Organization
Core
Define and own chip-level and IP-level ESD and latch-up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces to ensure product reliability from design through manufacturing.
Role type
Staff ESD/Latch-up Engineer (HBM Design Architecture)
Builds
Next-generation High Bandwidth Memory (HBM) solutions for AI and machine learning
Domain
Semiconductor / Memory Technology / ESD Physics
Deliverable
production ML models
Required skills
ESD physics fundamentals, latch-up mechanisms, advanced CMOS devices, ESD protection circuit design, latch-up prevention techniques, JEDEC/ESDA standards knowledge, silicon validation, failure analysis, foundry partnership management
Preferred skills
HBM/DRAM ESD sign-off experience, SCR-based clamp design, distributed ESD networks, rail-based strategies, foundry ESD team collaboration, technical mentorship
Technologies
HBM, DRAM, TSV, CDM, JESD78, SCR clamps
Responsibilities
Define chip-level and IP-level ESD and latch-up strategies; Establish ESD and latch-up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards; Enable ESD protection circuits and latch-up safe layout practices; Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results; Act as the technical interface to foundries and partner with design, packaging, reliability, and product teams
Seniority
Staff, hands-on IC with mentorship
