Digital Design Engineer, DMTS/SMTS/MTS
Core
Design, develop, and deliver high-quality RTL for complex DRAM, memory, and mixed-signal digital blocks, driving projects from architecture and specification through implementation handoff.
Role type
Senior IC digital design engineer (front-end ASIC)
Builds
High-performance DRAM, NAND, NOR memory and storage products
Domain
Semiconductor / Memory and Storage
Required skills
RTL design, microarchitecture development, Verilog, SystemVerilog, timing closure, static timing analysis (STA), logic synthesis, low-power implementation methodologies, EDA tools, CMOS digital and mixed-signal concepts
Preferred skills
AI-assisted engineering technologies, generative AI tools, automation frameworks
Technologies
Verilog, SystemVerilog, SDC, UPF, EDA tools
Responsibilities
Design and develop RTL for complex digital blocks; own front-end ASIC design activities including linting, CDC/RDC verification, and timing closure; develop and optimize design constraints and power intent; collaborate with architecture, verification, and physical implementation teams; analyze synthesis and timing reports to drive design improvements; enhance design methodologies and automation flows; champion continuous improvement initiatives using AI tools.
Seniority
Senior, hands-on IC
