Staff Engineer IP Verification - Digital Design Verification
Core
Lead verification efforts for strategic IPs and complex subsystems in DDR5, LPDDR5, DDR6, and LPDDR6 memory technologies operating at high speeds up to 11,4000MT/s.
Role type
Staff-level IC digital design verification engineer
Builds
Custom block-level memory designs for high-performance DRAM architectures
Domain
Semiconductor / Memory Storage / Digital Design
Required skills
RTL verification, SV-UVM methodology, directed and constrained-random testing, functional coverage analysis, RTL debugging, Perl scripting, Python scripting, digital circuit understanding
Preferred skills
AI tool integration for verification workflows, cross-functional leadership, mentoring junior engineers
Technologies
SV, UVM, Virtuoso, Xcellium, Simvision, Verdi/Verisium
Responsibilities
Define verification scope and strategy for block/chip RTL; develop and maintain verification testbenches and test vectors; run regressions and analyze results to close coverage metrics; debug RTL/testbench issues and partner with design engineers; provide verification status and risk summaries to stakeholders
Seniority
Staff, hands-on IC with technical leadership
