Senior Layout Designer
Core
Design and optimize semiconductor manufacturing products and processes to ensure cost, quality, reliability, and time-to-market efficiency.
Role type
Senior IC physical design engineer (analog/standard cell)
Builds
Memory and storage solutions for the semiconductor industry
Domain
Semiconductor manufacturing and VLSI design
Deliverable
production ML models | product features
Required skills
CMOS circuit design, VLSI layout, Cadence Virtuoso, LVS/DRC verification, analog layout techniques, place and route, layout synthesis
Preferred skills
AI-enabled floor planning tools, innovative process improvement approaches
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Collaborate with Design Engineering, Product Engineering, Process Integration, Probe, and Assembly groups; proactively design products optimizing manufacturing functions; utilize AI tools for layout floor planning and place and route; apply standard cell construction and analog layout techniques.
Seniority
Senior, hands-on IC
