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SR ENGINEER, DPG ARCHITECTURE STRATEGY

San Jose, CA💼 Full-time💰 $170,604–$170,604🗓 2026-08-19 → 2026-09-26

Core

Develop hardware models, validation test benches, and automation scripts for LPDRAM features and memory controllers to enable new DRAM technologies.

Role type

Senior IC computer architecture engineer (memory systems)

Builds

LPDRAM hardware models, memory controller simulations, and validation test benches

Domain

Semiconductor / Memory Technology

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

C/C++, Python, LPDRAM technology, Computer Architecture, Memory controller design, Cache policy, Simulation methodologies, Debugging interfaces (GDB, PDB)

Preferred skills

null

Technologies

Python, GDB, PDB

Responsibilities

Develop hardware models for DRAM features and validation test benches; Develop memory controller models including request scheduling and address mapping; Develop automation test scripts to improve simulation methodologies; Design and conduct hardware or software tests; Evaluate existing systems to determine effectiveness and suggest changes.

Seniority

Senior, hands-on IC

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