Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect
Core
Architecting next-generation SoC Fabric, System Cache, and DRAM Controller subsystems to optimize power, performance, and area for Samsung Galaxy devices.
Role type
Senior IC SoC Architect (Memory Subsystem and Interconnect)
Builds
High-performance SoC architectures for smartphones, tablets, and future Samsung Galaxy devices.
Domain
Semiconductor / Computer Architecture / Memory Systems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC or ASIC design and architecture, Fabric/System Cache/DRAM controller microarchitecture, memory controller architecture and scheduling, ARM bus infrastructure (ACE/AXI/AHB), JEDEC standards (LPDDR, DDR, HBM), performance modeling and simulation, silicon bring-up and debugging
Preferred skills
BookSim Simulator, Platform Architect
Technologies
ARM ACE/AXI/AHB, LPDDR, DDR, HBM, BookSim, Platform Architect
Responsibilities
Guide development of innovative Fabric, System cache, and DRAM controller architectural and microarchitectural features; Identify and deliver subsystem architecture proposals for new and existing markets; Evaluate architecture proposal benefits and communicate results across engineering audiences; Perform high-level performance modeling, simulation, and analysis of subsystem features; Direct and orchestrate performance studies to support feature inclusion in microarchitecture; Deliver architecture/microarchitecture proposals and specifications to design teams; Collaborate with silicon bring-up and product teams to verify and debug proposals; Collaborate across teams to bring microarchitectural proposals to fruition through detailed documentation
Seniority
Senior, hands-on IC
