Principal Engineer, ASIC Analog Design
Core
Design analog sub-blocks within High speed PHY for next-generation memory and storage solutions.
Role type
Principal Engineer, ASIC Analog Design
Builds
High speed PHY analog sub-blocks for 12nm and below technology nodes
Domain
Semiconductor / Memory and Storage / Analog IC Design
Deliverable
production ML models | product features
Required skills
Analog sub-block design, High speed PHY implementation, Specification definition, Implementation, 12nm and below node experience
Preferred skills
AI assisted design workflow knowledge
Technologies
12nm and below technology nodes
Responsibilities
Take ownership of analog sub-blocks inside the High speed PHY, drive the specification and implementation
Seniority
Principal, hands-on IC
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