Senior Engineer - CMOS & Metallization Test Structure Design and Layout
Core
Design, layout, and verify electrical test structures (TEGs) for CMOS device development, compact modeling, reliability, and fab process monitoring.
Role type
Senior IC semiconductor test structure design engineer
Builds
Silicon test structures and test element groups (TEGs) for memory and storage devices
Domain
Semiconductor manufacturing / Memory and storage (DRAM, NAND)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EDA tools (Cadence Virtuoso, Calibre), circuit build/layout/verification, DRC/LVS, circuit simulation (HSPICE), semiconductor device physics, DFM, DRAM/NAND architecture knowledge, parametric testing
Preferred skills
Perl/Skill/UNIX scripting, agentic AI solutions development
Technologies
Cadence Virtuoso, Calibre, HSPICE, Perl, Skill, UNIX
Responsibilities
Design and verify memory cell-based test structure solutions; Interpret DUT definitions and build TEGs with high confidence; Implement novel solutions to study failure mechanisms and monitor silicon health; Assist with parametric correlation and debug; Verify and validate test structure documentation; Leverage AI to reduce development time
Seniority
Senior, hands-on IC
