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DMTS Design Engineer

San Jose, CA💼 Full-time💰 $208,000–$208,000🗓 2026-07-08 → 2026-07-31

Core

Analyze current and next-generation memory technologies to identify performance gaps and guide future memory direction.

Role type

Distinguished Member of Technical Staff (DMTS) Design Engineer

Builds

Industry-leading DRAM products (DDR5, LPDDR, HBM, GDDR)

Domain

Semiconductor / Memory / DRAM Engineering

Deliverable

production ML models

Required skills

DDR memory architecture analysis, high-speed I/O evaluation, electrical margin assessment, memory power and thermal characteristics analysis, tradeoff evaluation, data-driven technical communication

Preferred skills

DDR4/5/LPDDR5/5X/5T/5T experience, memory controller architecture knowledge, firmware background, DRAM physical layout and packaging expertise, benchmarking and competitive analysis, memory modeling and system-level simulation

Technologies

DDR4, DDR5, LPDDR, HBM, GDDR, AI tools for data modeling

Responsibilities

Analyze memory technologies across electrical, thermal, power, and performance dimensions; Identify performance gaps and evaluate tradeoffs in cost, latency, bandwidth, and efficiency; Partner with architecture and product teams to translate analysis into actionable design guidance; Drive multi-functional alignment with firmware, validation, hardware, and business partners; Deliver clear technical assessments and recommendations to guide future memory strategy; Use Artificial Intelligence tools to build models to find design gaps and summarize collected data for distribution and analysis.

Seniority

Distinguished Member of Technical Staff (DMTS), Technical Leadership Program

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