Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Core
Build, enable, and scale characterization infrastructure for standard and custom cells to support High Bandwidth Memory (HBM) designs.
Role type
Design Infrastructure Engineer (Semiconductor Characterization)
Builds
Scalable characterization flows, Liberty models, and validation frameworks for HBM DRAM and logic dies.
Domain
Semiconductor / Memory / Heterogeneous Integration
Required skills
CMOS digital and mixed-signal circuit design, device physics, PVT variation analysis, Liberty modeling (CCS/ECSM), SPICE-based simulation, Static Timing Analysis (STA), Python/Perl/Tcl scripting, SiliconSmart, PrimeLib
Preferred skills
Multi-node semiconductor process experience, HBM/DRAM/high-speed interface design, TSMC PDK familiarity, High-speed PHY design, TSV-aware design, Signal integrity, EMIR effects, Aging and reliability modeling, Agentic AI
Technologies
Python, Perl, Tcl, SiliconSmart, PrimeLib, SPICE, STA, Liberty, TSMC PDKs
Responsibilities
Develop scalable infrastructure for standard and custom cell characterization including timing, power, noise, and signal integrity modeling; Build reusable automated flows for multi-corner multi-mode (MCMM) characterization and Liberty model generation; Enable characterization across heterogeneous process technologies (Micron internal and external foundries like TSMC); Support diverse HBM product verticals including core dies and advanced 3D architectures; Integrate characterization flows into design and verification ecosystems; Lead debug and validation efforts by root-causing mismatches between SPICE, extracted views, STA, and silicon behavior.
Seniority
Mid-Senior, hands-on IC
