Design Infrastructure Engineer (Standard and Custom Cell Characterization)-HBM
Core
Build scalable characterization infrastructure and deliver generated IP for standard and custom cell characterization across advanced memory and logic designs.
Role type
Design Infrastructure Engineer (Semiconductor Characterization)
Builds
Scalable characterization flows, Liberty models, and validation frameworks for HBM DRAM and logic dies.
Domain
Semiconductor manufacturing, High Bandwidth Memory (HBM), TSV technology, EDA infrastructure.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS digital and mixed-signal circuit design, device physics, PVT variation analysis, Liberty modeling (CCS/ECSM), SPICE-based simulation, Static Timing Analysis (STA), Python/Perl/Tcl scripting, SiliconSmart, PrimeLib
Preferred skills
Multi-technology process experience, HBM/DRAM/high-speed interface design, TSMC PDK familiarity, high-speed PHY design, TSV-aware design, Agentic AI workflow development
Technologies
Python, Perl, Tcl, SiliconSmart, PrimeLib, SPICE, STA, Liberty, TSMC PDK
Responsibilities
Develop and maintain scalable infrastructure for standard and custom cell characterization including timing, power, noise, and signal integrity modeling; Build reusable, automated flows for multi-corner, multi-mode characterization across PVT spaces; Enable characterization across heterogeneous process technologies including Micron internal nodes and external foundries like TSMC; Support characterization requirements for HBM product verticals including core dies and custom base dies; Integrate characterization flows into design and verification ecosystems by partnering with design, verification, and CAD teams; Lead debug, validation, and continuous improvement efforts by root-causing mismatches between SPICE, extracted views, STA, and silicon behavior
Seniority
Mid-Senior, hands-on IC
