Custom HBM Architecture and Design Engineer
Core
Architect, design, and implement RTL for next-generation HBM SoC logic die, focusing on memory sub-systems, IP integration, and system-level optimization for AI/ML workloads.
Role type
Senior IC Custom HBM Architecture and Design Engineer
Builds
High-performance HBM SoC logic die and memory sub-systems
Domain
Semiconductor / High-performance Memory / AI/ML Hardware
Deliverable
production ML models | product features
Required skills
SystemVerilog/Verilog, SoC integration methodologies, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), Python/TCL/Perl scripting
Preferred skills
HBM/DRAM memory-centric SoC design, high-speed interfaces and clocking strategies, DFT concepts (scan/MBIST), hardware emulation platforms
Technologies
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, Palladium, Veloce, Zebu
Responsibilities
Analyze hardware/software interaction to identify AI/ML workload bottlenecks; Architect and design memory sub-systems including IP selection and power/performance/area optimization; Integrate internal and third-party IP (controllers, NOC, RAS, PHY-adjacent logic); Translate architectural specifications into high-quality RTL implementations; Participate in SoC-level integration (clocking, reset, power intent); Assist with pre/post-silicon validation and root-cause analysis; Collaborate with Product Engineering, Test, and Manufacturing teams
Seniority
Senior, hands-on IC
