Director, Custom HBM Design and Architecture
Core
Lead a team in designing, integrating, and delivering next-generation HBM SoC logic die for AI/ML applications.
Role type
Director, Custom HBM Design and Architecture
Builds
Next-generation HBM SoC logic die for AI/ML applications
Domain
Semiconductor / High Bandwidth Memory (HBM) / AI/ML Hardware
Deliverable
production ML models
Required skills
SoC design leadership, RTL design, SoC integration, RTL-to-GDS flows, IP subsystem integration, SystemVerilog, Python, TCL, pre-silicon validation, hardware emulation, post-silicon debug
Preferred skills
DRAM/HBM systems knowledge, JEDEC standards, global engineering team management, tape-out program leadership
Technologies
SystemVerilog, Python, TCL, TSMC process nodes
Responsibilities
Analyze hardware/software interaction to identify AI/ML workload bottlenecks; Drive future HBM architecture and proof of concept designs; Translate architectural specs into RTL implementations; Own RTL design deliverables from development to silicon bring-up; Drive trade-offs across performance, power, area, schedule, and risk; Build and scale high-performing RTL design teams
Seniority
Director, technical leadership & team management
