Sr Memory Layout Engineer-DPG-LPDDR
Core
Designing and implementing high-performance memory array layouts for LPDDR DRAM solutions to accelerate data-to-intelligence transformation.
Role type
Senior IC memory layout engineer (LPDDR/DRAM)
Builds
Custom memory array layouts and decoder blocks for high-performance DRAM products
Domain
Semiconductor manufacturing / VLSI / Memory technology
Deliverable
production ML models | product features | infrastructure
Required skills
Bit cell layout creation, pitch matching, Row/Column decoder layout development, full-custom layout development, Cadence Virtuoso, Calibre DRC/LVS, DRAM/LPDDR architecture, device physics, transistor matching, well and substrate engineering, parasitic optimization, EM/ESD reliability
Preferred skills
AI/ML for layout automation and optimization
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Create bit cell layouts and match pitch; develop row and column decoder layouts; optimize layouts for power, schedule, and quality; apply device physics for transistor matching and reliability; independently plan and deliver layout blocks
Seniority
Senior, hands-on IC