E5_MTS_SMTS NAND Design Rule Engineer in Process Integration
Core
Develop and support high-volume manufacturing of advanced 3D NAND technologies by driving design-rule and PDK deliverables.
Role type
Senior IC NAND Design Rule / Process Integration Engineer
Builds
Design rules, PDKs, and mask definitions for R&D and production 3D NAND designs
Domain
Semiconductor manufacturing, 3D NAND, Process Integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor device physics, VLSI silicon processing and integration flow, PDK and design rule management, CAD tool proficiency (Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE), 3D NAND process flow knowledge, test structure design and evaluation, complex issue resolution, cross-functional coordination
Preferred skills
R&D experience in NAND or other memory technologies
Technologies
Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE
Responsibilities
Lead release of design rules and PDK deliverables; manage DRC waivers and mask reviews; own program execution from kickoff to end-of-life; partner with process integration and design organizations to guide new 3D NAND generations; ensure quality and documentation for DRCs; collaborate with yield enhancement and defect analysis to identify and resolve process issues; design and evaluate test structures for next-generation devices; define and track sub-milestones within PDK/DBR/TO schedules; drive continuous improvement in design-rule pathfinding
Seniority
Senior, hands-on IC