MTS ASIC Architect
Core
Define silicon-level architectures for high-bandwidth, energy-efficient, and scalable DRAM products, balancing trade-offs across silicon, packaging, and system integration.
Role type
Senior IC ASIC Architect (Memory)
Builds
Scalable, reliable, high-performance DRAM memory solutions
Domain
Semiconductor / Memory / DRAM
Deliverable
production ML models | product features | infrastructure
Required skills
DRAM die architecture, ASIC logic design, micro-architectural decision making, PPA evaluation, RTL design review, signal integrity analysis, thermal management, interface protocol definition, cross-functional technical leadership
Preferred skills
Master's or PhD in EE/CS, experience with high-speed interfaces, knowledge of JEDEC standards, system-level tradeoff analysis, multi-project technical leadership
Technologies
DRAM silicon, ASIC logic, RTL, high-speed interfaces, packaging technologies
Responsibilities
Define ASIC and logic architectures enabling high data throughput and efficient parallelism; Lead architectural trade-off analyses across silicon, packaging, and system integration; Influence functional partitioning and interface definitions; Drive architectural analysis including PPA evaluation and timing considerations; Perform micro-architectural and design reviews to ensure first-silicon success; Serve as technical mentor and architectural authority for execution teams
Seniority
Senior, hands-on IC