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Principal Design Engineer, DRAM

Boise, ID - Main Site💼 Full-time🗓 2026-07-08 → 2026-07-31

Core

Developing, analyzing, and optimizing circuit designs for next-generation memory technologies.

Role type

Principal Design Engineer (semiconductor memory circuits)

Builds

Memory arrays, control logic, address decode, datapath, and internal test logic for DRAM products

Domain

Semiconductor industry, memory and storage solutions

Deliverable

production ML models | product features

Required skills

Semiconductor circuit design, layout, and optimization; Circuit simulation (SPICE); Hardware description languages (VERILOG); Device specification interpretation; Component evaluation and modification

Preferred skills

Memory architecture design; CMOS device behavior analysis; Reliability engineering; Test chip definition; Silicon validation support; AI application in circuit design

Technologies

SPICE, VERILOG

Responsibilities

Design and optimize memory circuits from gate-level to full chip implementations; Lead development of schematic blocks; Perform advanced circuit simulations; Drive architectural decisions for power, speed, and die area; Collaborate on design rules and validation strategies

Seniority

Principal, hands-on IC with leadership

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