DRAM Memory Design Engineer - Principal | MTS | SMTS
Core
Design and optimize next-generation DRAM products (memory arrays, control logic, datapaths, address decoding, I/O circuitry) balancing performance, power, quality, and reliability.
Role type
Principal Semiconductor Design Engineer (DRAM)
Builds
High-performance memory solutions for AI accelerators, mobile, and client devices
Domain
Semiconductor / Memory Technology
Deliverable
production ML models | product features
Required skills
CMOS circuit design, device physics, state machine logic, Verilog modeling, simulation tools, power delivery network (PDN) analysis, scripting (Python/Tcl/Perl), floor-planning, layout optimization, tape-out activities
Preferred skills
DDR5/LPDDR5/6, GDDR6/7, HBM3/4 memory technologies, FINESIM/HSPICE, leading complex circuit design projects, AI/ML-assisted design flows, agentic AI, advanced design automation frameworks
Technologies
Verilog, Python, Tcl, Perl, FINESIM, HSPICE
Responsibilities
Design and optimize digital and analog circuits for next-generation DRAM products; Lead circuit development, simulation, verification, and silicon validation; Drive floor-planning, layout optimization, parasitic analysis, and tape-out activities; Advance AI-assisted design and automation; Provide technical leadership and mentorship
Seniority
Principal, hands-on IC with technical leadership