Design Verification Engineer
Core
Entry-level Design Verification Engineer building testbenches and constrained-random tests for next-generation interconnect and chassis IPs.
Role type
Entry-level IC design verification engineer
Builds
Verification testbenches and simulation environments for interconnect and chassis IP
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Algorithmic thinking, clean code writing, logic design fundamentals, RTL reasoning, C/C++/Python/SystemVerilog proficiency, AI coding assistant usage
Preferred skills
UVM concepts, assertion-based verification, standard bus protocols (AXI, AHB, PCIe), Linux environment usage, git version control, build/test automation scripting
Technologies
SystemVerilog, UVM, ModelSim, VCS, Questa, C, C++, Python, Linux, git
Responsibilities
Develop testbench components and functional checkers; write, run, and debug simulation tests; analyze failures and root-cause issues; contribute to functional coverage plans and regression triage; participate in spec reviews and design discussions
Seniority
Entry-level, hands-on IC
