Chassis IP Senior Design Engineer
Core
Design and develop logic for component and foundation IPs used to build System-on-Chip (SoC) chassis, including high-performance routers, switches, and protocol bridges.
Role type
Senior IC logic design engineer (SoC chassis IP)
Builds
Logic designs, RTL code, and simulation models for interconnect IP blocks and subsystems
Domain
Semiconductor / SoC Design / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, System Verilog, RTL development, digital design principles, timing analysis, power optimization, area trade-offs, EDA tools (Synopsys, Cadence, Mentor Graphics)
Preferred skills
AMBA protocols (CHI, AXI, AHB, APB), PCIe/CXL protocols, SoC integration, physical design collaboration, AI-assisted design
Technologies
Verilog, System Verilog, Synopsys, Cadence, Mentor Graphics
Responsibilities
Develop logic designs and RTL coding for functional units and IP blocks; Define and implement architecture for interconnect IP including routers, switches, and protocol bridges; Perform quality checks and optimization for power, performance, area, and timing; Evaluate design trade-offs for efficiency; Support SoC customers with IP integration workflows
Seniority
Senior, hands-on IC
