Senior Density Fill Development Engineer
Core
Design, develop, and debug Fill components of Process Design Kits (PDKs) and provide algorithmic solutions to address density deficiencies and ensure manufacturability compliance for Intel's hardware product design and manufacturing processes.
Role type
Senior IC EDA Tools Software Engineer (Density Fill)
Builds
Process Design Kits (PDKs) and physical verification rule decks for advanced semiconductor nodes
Domain
Semiconductor manufacturing / Physical Verification / Design Automation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical verification platforms (Calibre, ICV, Pegasus), SVRF/TVF/PXL/PVL/PVTCL rule deck development, semiconductor device physics, algorithmic solutions for physical design, Unix/Linux environments
Preferred skills
Density fill methodologies at 16nm and below, advanced physical verification techniques (DRC, density/fill modules), custom layout tools (Cadence Virtuoso, Synopsys Custom Designer), technology scaling challenges, cross-functional collaboration
Technologies
Calibre, ICV, Pegasus, SVRF, TVF, PXL, PVL, PVTCL, Cadence Virtuoso, Synopsys Custom Designer
Responsibilities
Design and debug Fill components of PDKs; Provide algorithmic solutions for density deficiencies; Collaborate with process developers and design rule owners; Automate workflows for design teams; Develop test cases to validate software tools; Partner with cross-functional teams and external EDA vendors; Maintain documentation and training materials
Seniority
Senior, hands-on IC
