Sr. EDA Tools Engineer - PERC ESD
Core
Develop PERC ESD rule decks and reliability design rule methodologies for Intel's latest process technologies to enable faster time-to-market for design teams.
Role type
Senior IC EDA Tools Engineer (Physical Design Verification)
Builds
ESD/LU rule decks, runsets, and verification automation tools for Intel PDKs
Domain
Semiconductor manufacturing / Process Design Kit (PDK) / Physical Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ESD/LU rule deck development, reliability design rule methodologies, ESD Design Rule Manual (DRM) alignment, test case creation and execution, QA automation, root cause analysis, cross-functional collaboration
Preferred skills
ESD/LU PreSi models (HBM, CDM) knowledge, I/O design expertise, cross-disciplinary solutioning, stakeholder influence
Technologies
Python, Tcl, Perl, ESD verification tools, DRC tools
Responsibilities
Develop ESD/LU rule decks aligned with DRM and reliability requirements; Create and maintain reliability ESD and LU design rule methodologies; Collaborate with internal design, reliability, and CAD teams to define tool features; Build and execute test cases for rule debugging and validation; Define QA requirements and drive automation for rule checks; Lead innovation initiatives for verification automation; Identify and analyze ESD/LU design problems to drive solutions
Seniority
Senior, hands-on IC
