Analog Layout Design Engineer
Core
Design complex layouts for analog signal circuits, ensuring optimization for performance, area, and reliability while meeting stringent design specifications.
Role type
Analog Layout Design Engineer
Builds
Analog and mixed-signal circuit layouts for Intel's cutting-edge semiconductor technologies
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog device and metal layout fundamentals, Cadence Virtuoso Layout Suite, Calibre/ICV DRC, CMOS technologies, high-voltage rules, floor planning, hierarchical layout planning, performance verification, layout debugging
Preferred skills
Analog layout effects analysis (mismatch, parasitics, IR drop, electromigration, coupling), symmetry-based layout techniques, process variation mitigation, parasitic-aware design, LVS correlation, noise isolation and signal integrity optimization
Technologies
Cadence Virtuoso, Calibre, ICV, xtract, spef
Responsibilities
Design complex analog circuit layouts based on specifications; conduct design verification checks (DRC, EM, IR drop, ESD); develop floorplans, power grids, and ESD structures; perform signal planning for optimization; troubleshoot design and tool issues; collaborate with cross-functional teams on layout tradeoffs
Seniority
Mid-Senior, hands-on IC
