Mixed Signal Logic Design Engineer
Core
Designing high-speed, low-power digital logic for DDRPHY IPs within Intel's Central Engineering Group.
Role type
Senior IC Mixed Signal Logic Design Engineer
Builds
DDRPHY IP blocks for Intel's product and foundry businesses
Domain
Semiconductor / Memory Interface / Digital Logic
Deliverable
production ML models | product features
Required skills
System Verilog, Verilog, Mixed Signal fundamentals, Low-power design (UPF, clock gating), Digital design principles, Analog design principles, Clock domain crossing, Hardware simulation (VCS/Verdi), IP configuration management, Front End design tools (Lint, CDC, RDC, Synthesis)
Preferred skills
Complex logic debugging, System-level validation, Mentorship, DFI/DDR/LPDDR protocols, AI-assisted coding (VSCode CoPilot), Formal Property Verification, Git, Pre-silicon/post-silicon validation, Analog-Digital tradeoff optimization
Technologies
System Verilog, Verilog, VCS, Verdi, UPF, Git, VSCode
Responsibilities
Define architecture and microarchitecture for logic blocks; Implement RTL and set up automation flows; Ensure RTL quality via linting and timing checks; Collaborate with validation and backend teams to deliver IP milestones; Drive improvements in turnaround time, robustness, area, and power metrics.
Seniority
Senior, hands-on IC
