Staff Digital Design Engineer
Core
Architecting and designing power and area optimized digital circuits for complex mixed-signal applications including data conversion and power management.
Role type
Staff Digital Design Engineer (ASIC/SoC)
Builds
Mixed-signal data conversion and power management silicon solutions
Domain
Semiconductor / Embedded Systems / Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design (Verilog/SystemVerilog), ASIC design methodology, Mixed-signal design flow, Timing closure (STA), Low-power design techniques (UPF, clock/power gating), Block-level & chip-level verification, Debugging RTL & gate-level simulations, Design constraints generation, P&R interaction, DFT strategy, Protocol knowledge (AMBA, I2C)
Preferred skills
Digital Signal Processing (DSP) concepts, Flow automation scripting, Behavioral modeling (AMS)
Technologies
Verilog, SystemVerilog, UVM, UPF, AMBA, I2C
Responsibilities
Interpret high-level requirements to architect low-power digital circuits, Design digital RTL meeting timing/area/power specs, Integrate designs and run block/top-level simulations, Mentor junior engineers and lead technical discussions, Develop design documents and participate in design reviews, Support DFT strategy and test-case development
Seniority
Staff, technical leadership & mentorship
