Senior Design Verification Engineer
Core
End-to-end verification of critical chassis and interconnect IP blocks from planning through signoff, ensuring quality in testbench architecture and coverage closure.
Role type
Senior IC Design Verification Engineer (Silicon/SoC)
Builds
Scalable verification environments, reusable test benches, checkers, VIPs, and behavioral models for IP and subsystem integration.
Domain
Semiconductor / Silicon Design / Interconnects & Memory Subsystems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog/UVM, C/C++, Python, AMBA (CHI, ACE, AXI), PCIe, UCIe, CXL, cache coherency, memory consistency, simulation and formal verification, low-power verification, HDL/verification languages, EDA tools, RTL, physical design, CAD tool flows
Preferred skills
Formal verification tools (JasperGold, VC Formal), emulation or FPGA-based verification, system IPs (MMUs, interrupt controllers), associated software stacks
Technologies
UVM, SVA, ABV, JasperGold, VC Formal, SystemVerilog, C, C++, Python, AMBA, PCIe, UCIe, CXL
Responsibilities
Own verification planning and execution for key IP features; Build scalable verification environments with reusable collateral; Collaborate with architecture, design, and software teams; Drive ownership of critical blocks and functional signoffs; Lead IP delivery to multiple customers; Drive convergence of simulation and formal verification; Mentor verification engineers and establish best practices
Seniority
Senior, hands-on IC
