Analog Mixed Signal Design Engineer
Core
Senior Mixed Signal Design Engineer driving static timing analysis (STA) and design closure for next-generation mixed-signal systems at Intel.
Role type
Senior IC mixed-signal design engineer (verification & STA focus)
Builds
Mixed-signal IP and systems for Intel's product and foundry businesses
Domain
Semiconductor / Mixed-signal circuit design
Deliverable
production ML models | product features
Required skills
Static timing analysis (STA), Analog circuit design, Mixed-signal verification, Python scripting, Cadence ADE, Behavioral modeling (Verilog-A, SystemVerilog), Root-cause analysis, Automation
Preferred skills
SerDes or PLLs experience, Analog behavioral modeling, AI-driven automation, Mixed-signal design principles
Technologies
Cadence ADE, Python, Verilog-A, SystemVerilog
Responsibilities
Lead STA execution for mixed-signal designs; Execute analog circuit design tasks including simulation setup and testbench development; Investigate and resolve complex issues in analog testbenches; Develop behavioral models to improve simulation accuracy; Drive timing optimization and constraint development
Seniority
Senior, hands-on IC