High-Speed SerDes Simulation & Optimization Intern — I/O Next Generation R&D
Core
Intern supporting readiness and scalability for next-generation high-speed I/O technologies (PCIe, UPI, CXL, USB) by developing automated simulation workflows and analyzing channel performance.
Role type
Intern, high-speed I/O simulation engineer
Builds
Automated simulation workflows for PCIe channel/circuit topologies
Domain
Semiconductor / Data Center / High-Speed Serial Links
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Electrical engineering (digital and analog), channel model extraction (S-parameters), equalization sweeps (TX FIR/FFE, CTLE/DFE), simulation tool usage, scripting for automation (Python/MATLAB), data analysis
Preferred skills
High-speed serial link fundamentals, ICAT/Seasim simulation environments, VNA/TDR concepts, PCIe channel building blocks knowledge
Technologies
ICAT, Seasim, Python, MATLAB
Responsibilities
Develop automated end-to-end simulation workflows for PCIe channel/circuit topologies; Extract realistic channel models from full topology descriptions; Set up and run transmitter/receiver equalization sweeps; Analyze simulation outputs to identify performance bottlenecks; Automate post-processing, data reduction, and reporting; Deliver reusable simulation testbench and technical report; Present progress and findings in team meetings
Seniority
Intern
