Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING
Core
Leading the end-to-end design and delivery of next-generation processor and SoC IP solutions from architectural specification through tapeout.
Role type
Senior Manager / Deputy Director, Processor Design
Builds
High-performance and low-power processor cores, subsystems, and SoC IP
Domain
Semiconductor / ASIC Digital Design
Deliverable
production ML models | product features
Required skills
Microarchitecture development, RTL design (Verilog/SystemVerilog), Processor pipelines, Memory subsystems, SoC integration, ASIC design flow, Synthesis and timing analysis, PPA optimization, Team leadership, Project management
Preferred skills
RISC-V/MIPS/ARM/ARC architecture experience, Advanced technology nodes (7nm/5nm/3nm), Multicore processors, AI accelerators, High-performance computing architectures, Geographically distributed team leadership
Technologies
Verilog, SystemVerilog, RISC-V, MIPS, ARM, ARC, 7nm, 5nm, 3nm
Responsibilities
Lead end-to-end development of processor cores from spec to tapeout, Drive microarchitecture definition and RTL implementation, Review design specifications and timing closure strategies, Develop project plans and track design milestones, Build and mentor high-performing engineering teams, Coordinate with cross-functional teams for PPA targets
Seniority
Senior Manager / Deputy Director, hands-on IC leadership
