PMTS, Design Verification Lead
Core
Lead verification strategy, planning, execution, and signoff for next-generation RISC-V based Processor IP products, ensuring functional correctness, quality, performance, safety, and robustness of complex processor subsystems and full-chip IP solutions.
Role type
Senior IC design verification lead (processor architecture)
Builds
Production-ready RISC-V processor IP, CPU cores, DSP extensions, vector processing units, MMUs, caches, and security features
Domain
Semiconductor / Processor Architecture / ASIC/SoC
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Assertions (SVA), Functional Coverage, Constrained Random Verification, Processor Architecture, Microarchitecture, Simulation/Emulation/Regression Infrastructure, Coverage-driven Verification, Verification Signoff Methodologies
Preferred skills
RISC-V processors, Vector extensions, DSP architectures, Functional safety (ISO 26262, ISO 21434), Cyber Security, Formal verification, FPGA prototyping, Performance verification, Software-driven verification, Building verification environments from scratch
Technologies
SystemVerilog, UVM, SVA, RISC-V, ARM, FPGA, Emulation platforms
Responsibilities
Own verification strategy and signoff for processor IP; Architect scalable verification environments; Lead verification of CPU cores, DSP, vector units, MMUs, caches, and security features; Drive bug triage and root-cause analysis; Present status and signoff readiness to executive leadership; Mentor verification engineers across multiple projects
Seniority
Senior, hands-on IC with team leadership
