Principal Engineer SoC Design Verification
Core
Define and drive verification strategy, methodology, planning, execution, and signoff for complex Smart Analog & Sensor SoCs to ensure first-pass silicon success.
Role type
Principal SoC Verification Lead (Strategy & Technical Leadership)
Builds
Complex Smart Analog & Sensor SoCs for MIPS by GF Custom Silicon Business
Domain
Semiconductor / SoC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM-based verification, SoC verification strategy, verification environment development, coverage closure methodology, team leadership, cross-functional coordination, verification signoff, automation development
Preferred skills
Emulation and prototyping, safety and security verification, performance verification, leading globally distributed teams
Technologies
UVM, SoC verification frameworks, coverage metrics tools
Responsibilities
Define verification architecture for complex SoCs; Lead development of UVM-based verification environments; Coordinate subsystem and SoC-level verification activities; Mentor senior verification engineers; Drive closure of functional, code, and assertion coverage; Establish signoff criteria and coverage closure methodology
Seniority
Principal, strategy & mentorship
