Digital Design Engineer
Core
Develop, document, and maintain RTL for digital subsystems within co-packaged optical modules (CPO), including control logic, register interfaces, link management, and DFT structures.
Role type
Digital Design Engineer (RTL)
Builds
Digital subsystems for co-packaged optical modules (CPO)
Domain
Semiconductor / Silicon Photonics / Co-packaged Optics
Required skills
RTL design (SystemVerilog/Verilog), digital design fundamentals (synchronous design, CDC, FSMs, pipelining, low-power), EDA tools (synthesis, lint, CDC, simulation), scripting (Python, TCL, Perl), UVM verification
Preferred skills
High-speed serial interfaces (SerDes, PCIe, Ethernet, CXL), silicon photonics, co-packaged optics, ARM-based SoC integration, AMBA protocols (AXI/AHB/APB), UPF/low-power flows, DFT (scan, MBIST, boundary scan)
Technologies
SystemVerilog, Verilog, UVM, Python, TCL, Perl, EDA tools
Responsibilities
Develop and maintain RTL for digital subsystems; Collaborate with architecture, analog/mixed-signal, and photonics teams; Own micro-architecture specifications and IP integration; Drive synthesis, timing closure, CDC, lint, and low-power sign-off; Perform FPGA prototyping and testing; Develop and execute UVM-based testing; Support verification efforts; Participate in tape-out readiness activities
Seniority
Entry-level to Mid-level, hands-on IC
