Physical Design Lead (PnR, STA)
Core
Develop digital design enablement collateral and RTL2GDS flows to help customers adopt advanced semiconductor technologies (12/14/22/28/40/55nm).
Role type
Senior IC physical design methodology engineer
Builds
Digital design flows (Synthesis, Place and Route, Extraction, Timing, Physical Verification) for semiconductor PDKs
Domain
Semiconductor manufacturing / Digital IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL2GDS flow creation, Synthesis, Place and Route, Parasitic extraction, Static timing analysis, Physical verification, EDA tool scripting (TCL, Python), PDK qualification, Cross-tool PPA benchmarking, Testcase generation
Preferred skills
Low power design (UPF), Liberty format parsing, Version control (Perforce), Java, SQL
Technologies
Synopsys ICC/ICC2, Cadence EDI/INNOVUS, Mentor OlympusSoC, TCL, Python, Pandas, Google APIs, Perforce
Responsibilities
Create and qualify RTL2GDS flows for synthesis, place and route, extraction, timing, and physical verification; Collaborate with EDA vendors and PDK teams to define and customize digital design flows; Develop automation scripts for flow regression and error analysis; Perform cross-tool and PDK PPA benchmarking using reference flows; Define and generate design testcases to measure PDK and technology changes
Seniority
Senior, hands-on IC
