Senior ASIC CAD Engineer
Core
Bridge frontend logic and physical design teams to deliver digital logic for next-generation firewall platforms.
Role type
Senior ASIC CAD Engineer
Builds
Digital logic for Palo Alto Networks firewall platforms
Domain
Cybersecurity hardware / ASIC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Logic synthesis, Static Timing Analysis (STA), Power optimization (UPF), Perl scripting, Python scripting, Tcl scripting, Linux Shell, SDC constraint formulation, Tape-out closure management
Technologies
Synopsys Design Compiler, Synopsys PrimeTime, Cadence Genus, Cadence Tempus
Responsibilities
Drive full-chip and block-level logic synthesis for optimal PPA; Formulate master timing constraints and execute sign-off STA; Implement low-power strategies using UPF; Act as technical liaison to external P&R ASIC vendors; Develop automation scripts for design flows; Maintain ASIC CAD infrastructure
Seniority
Senior, hands-on IC