FPGA Design Engineer
Core
Specify and design FPGA RTL blocks (IP) for data handling and synchronization in complex communication networks.
Role type
Senior IC FPGA Design Engineer
Builds
Reusable RTL blocks and complete FPGA systems for high-performance communication networks
Domain
Semiconductor hardware design / Digital communications
Required skills
SystemVerilog, synchronous digital design, clock-domain crossing analysis, FPGA simulation, synthesis and timing analysis, Linux, Git, Python, C, requirements definition, trade-off analysis
Preferred skills
High-speed digital interfaces, reusable RTL development
Technologies
SystemVerilog, FPGA, Linux, Git, Python, C (via careerplan.io/jobs/J-00352789-fpga-design-engineer-at-asml)
Responsibilities
Design RTL blocks with robust exception handling and reset behavior; define, document and negotiate requirements; analyze design alternatives and perform trade-off studies; document RTL architecture and design decisions; collaborate on block and system-level issues; develop and execute hardware tests; contribute to technical roadmaps and development practices
Seniority
Senior, hands-on IC
