Sr Memory PHY Enablement
Core
Post-silicon validation and bring-up of HBM/DDR/LPDDR memory interface IP for AMD processors, ensuring stability and robustness across PVT conditions.
Role type
Senior IC memory PHY validation engineer
Builds
High-performance memory interface IP for AMD processors
Domain
Semiconductor / Memory Interface
Required skills
Memory PHY validation, digital design, processor architecture, test plan development, root cause analysis, emulation environments, PVT characterization, firmware debugging, Linux environments, scripting (Python), laboratory equipment operation (oscilloscopes, BERT, logic analyzers)
Preferred skills
Memory IP familiarity, Python programming, new toolset adoption
Technologies
HBM, DDR, LPDDR, Python, Linux, ATE, emulation environments, oscilloscopes, signal generators, BERT, logic analyzers
Responsibilities
Provide systems engineering and post-silicon support for memory interface IP; Support bring-up of new products from first silicon through initial production; Triage silicon validation observations and collaborate with cross-functional teams to resolve issues; Provide expertise in silicon design, process, and integration flows; Develop and run comprehensive test plans in emulation environments; Characterize memory PHY across PVT to validate functionality and optimize power/performance
Seniority
Senior, hands-on IC
