Design Verification Engineer
Core
Lead verification of complex networking IP, subsystems, and SoCs for data center, cloud, and enterprise infrastructure products.
Role type
Senior IC design verification engineer (networking silicon)
Builds
Networking silicon and software for data center, cloud, and enterprise infrastructure
Domain
Semiconductor / Networking hardware
Required skills
SystemVerilog, UVM, constrained-random verification, debug of architecture/RTL issues, performance verification, scripting (Python/Tcl/Shell/Perl), industry protocols (PCIe, Ethernet, DMA, AXI)
Preferred skills
Packet-processing pipelines, switch fabrics, formal verification, FPGA/HAPS validation, architectural modeling, C/C++ reference models
Technologies
VCS, Verdi/DVE, Python, Tcl, Make, HAPS
Responsibilities
Develop UVM-based testbench architectures; drive test plan creation and coverage strategy; verify networking functions (Ethernet, PCIe, DMA, packet processing); execute verification plans and debug complex failures; optimize simulations and coverage closure; mentor junior engineers
Seniority
Senior, hands-on IC
