RTL Design Engineer
Core
Design and verify block-level RTL IP and embedded microprocessor subsystems for AMD SoC products, focusing on security, cryptography, and performance.
Role type
Senior IC RTL Design Engineer
Builds
Embedded microprocessor subsystems and hardware accelerators for client, server, graphics, and gaming platforms
Domain
Semiconductor / Hardware Design
Required skills
Verilog, SystemVerilog, Python, Tcl, Perl, Ruby, Make, AXI, AHB, AMBA, ASIC flows, simulation, debug, linting, synthesis, timing analysis, power-aware verification
Preferred skills
CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, FPGA-based emulation, AI-powered RTL design methodologies, C-DPI based verification, technical leadership
Technologies
Verilog, SystemVerilog, Python, Tcl, Perl, Ruby, Make, AXI, AHB, AMBA, C-DPI
Responsibilities
Develop and maintain block-level RTL IP and MP subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies; Design, implement, and debug RTL solutions using AI-powered methodologies and verification testbenches; Analyze regression failures, debug simulations, and evaluate coverage results; Contribute to verification planning by defining test plans and promoting design-for-verification best practices; Debug and resolve subsystem and SoC integration issues; Provide technical leadership in IP architecture and RTL design methodologies
Seniority
Senior, hands-on IC
