Mask Layout Designer
Core
Design and verify sophisticated SRAM digital circuit layouts and macros for tape-out, collaborating with circuit teams to ensure quality and schedule adherence for AMD's product roadmap.
Role type
Senior IC mask layout engineer (digital/analog)
Builds
Mask layouts for SRAM circuits, macros, and tiles integrated at SOC level
Domain
Semiconductor manufacturing / Digital circuit design
Required skills
SRAM digital circuit design, DRC/LVS verification and debugging, mask design tools, tape-out processes, cross-functional collaboration, project leadership
Preferred skills
Analog/Mixed-signal design, scripting (Skill, Perl, TCL, Python), mentoring design teams, tool improvement initiatives
Technologies
Vendor-specific and in-house mask design tools, DRC/LVS checkers
Responsibilities
Design complete SRAM digital circuits, perform verification and checking from start to tape-out, collaborate with layout and circuit designers, lead major projects and resource allocations
Seniority
Senior, hands-on IC
