Design Verification Lead
Core
Lead design verification for next-generation PCIe and CXL-based IP solutions, ensuring first-pass silicon success for FPGA and ASIC products.
Role type
Senior IC design verification lead (PCIe/CXL)
Builds
High-speed connectivity IP for data center and AI infrastructure
Domain
Semiconductor / High-speed interface protocols
Required skills
UVM methodology, SystemVerilog, Verilog, PCIe/CXL protocol verification, Python/Perl scripting, regression test development, functional coverage analysis, technical leadership
Preferred skills
ASIC/FPGA lifecycle experience, performance verification, simulation optimization, HLS tools, AI-assisted verification, mentoring distributed teams
Technologies
UVM, SystemVerilog, Verilog, PCIe, CXL, Python, Perl, FPGA, ASIC
Responsibilities
Define and verify new PCIe, CXL, and high-speed connectivity features; Develop comprehensive verification plans; Design and implement UVM verification environments; Develop directed and constrained-random tests; Drive verification automation and methodology improvements
Seniority
Senior, hands-on IC with leadership
