ASIC Design Engineer, PCIe IP Enablement
Core
Design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows.
Role type
Senior IC ASIC Design Engineer (PCIe IP)
Builds
PCIe subsystems and IP deployed to SoC
Domain
Semiconductor / Hardware Design
Required skills
RTL design (Verilog HDL), Synthesis, Timing closure, Lint/CDC closure, Low power design (UPF), Test/Debug/Clocks, Flow automation/scripting, Subsystem integration (tile flow, repeaters, SRAM), DFT/DFD awareness
Preferred skills
Equivalence checks (LEC), Static Timing Analysis (STA), Version control systems, AI knowledge for skill development
Technologies
Verilog, UPF, Lint, CDC, LEC, STA, SoC
Responsibilities
Integrate and implement AMD PCIe subsystem and IP deployment to SoC; Perform synthesis, timing, lint, and CDC closure; Implement design related to test, debug, and clocks; Drive flow development, automation, and scripting; Collaborate with IP designers, Physical Design team, and SoC leads; Mentor engineers and lead technical direction
Seniority
Senior, hands-on IC with mentorship responsibilities
