Sr. Staff Physical Design Engineer
Core
Own and drive complex physical design work for multi-million-gate graphics IP blocks for next-generation AI data center chips, delivering against performance, power, and area targets.
Role type
Sr. Staff Physical Design Engineer (IC)
Builds
Graphics IP blocks for AI data center chips
Domain
Semiconductor / Physical Design
Deliverable
production ML models
Required skills
Physical design, floorplanning, synthesis, placement, clock tree synthesis, routing, timing closure, physical verification, DRC/LVS, EM/IR analysis, Python, TCL, advanced process technologies (N2P or below)
Preferred skills
RTL design, logic-level optimization, computer organization/architecture, AI techniques for optimization
Technologies
Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk, Cadence Innovus, Genus
Responsibilities
Own physical design of complex graphics IP blocks; Partner with RTL teams to address timing bottlenecks; Drive floorplanning, synthesis, placement, CTS, routing, extraction, and signoff; Perform DRC/LVS, crosstalk, and EM/IR analysis; Establish design methodologies and IP integration; Develop automated design flows; Provide technical leadership and mentoring.
Seniority
Sr. Staff, hands-on IC with mentorship
