PD Engineer
Core
Implement high-performance ASIC/SoC blocks from synthesis to tapeout, meeting timing, power, area, and reliability targets.
Role type
Senior IC physical design engineer (ASIC/SoC)
Builds
High-performance digital blocks (DDR, CPU, GPU, AI/ML, Networking, Data Center SoCs)
Domain
Semiconductor hardware design (VLSI)
Required skills
RTL-to-GDSII implementation, Floorplanning, Power Grid Design, Placement Optimization, CTS, Routing, ECO Implementation, Timing Closure, Static Timing Analysis (STA), DRC/LVS, Antenna Checks, Density Checks, UPF/CPF concepts, Power gating, Multi-voltage methodologies, Tcl, Perl, Python, Shell scripting
Preferred skills
Advanced technology nodes (16nm/7nm/5nm/3nm), Package and chiplet integration, Hierarchical and full-chip implementation flows
Technologies
Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, IC Validator, Cadence Innovus, Tempus, Voltus, Genus, Siemens/Mentor Calibre
Responsibilities
Perform physical implementation of digital blocks from netlist to GDSII, Analyze and close setup/hold timing violations, Signal Integrity issues, Crosstalk violations, IR Drop and Electromigration (EM), DRC/LVS violations, Debug physical design issues across advanced technology nodes
Seniority
Senior, hands-on IC
