Physical Design Lead(High Speed IP's)
Core
Lead physical design implementation of complex high-speed interface IPs (DDR, LPDDR, GDDR, PCIe, SerDes) and mixed-signal PHY solutions for client, server, and graphics products.
Role type
Senior Member of Technical Staff (PMTS), hands-on IC Physical Design Lead
Builds
High-performance high-speed interface IPs and mixed-signal PHYs for AMD processors
Domain
Semiconductor / Advanced Process Nodes / High-Speed Digital & Mixed-Signal
Required skills
Physical design implementation, high-speed interface IP expertise, timing closure, clock distribution, EMIR, clock tree, physical verification, EDA tool expertise (Cadence, Synopsys), methodology development, automation, cross-functional leadership, mentoring
Preferred skills
Tape-out experience on N3/N4/N5 nodes, leadership across geographies, AI-assisted design methodologies
Technologies
Cadence, Synopsys, N3/N4/N5 process nodes
Responsibilities
Lead physical design implementation of complex high-speed IPs, own end-to-end implementation activities, drive high-frequency timing closure, partner with architects to optimize PHY architectures, develop innovative implementation methodologies, collaborate with cross-functional teams, provide technical leadership, mentor junior engineers, drive continuous improvement in automation and signoff flows
Seniority
Senior, hands-on IC with leadership responsibilities
