Sr DFT/ATPG Engineer–Mixed-Signal IP
Core
Own scan architecture and validation strategy for analog and mixed-signal intellectual property (IP), delivering production-quality test patterns and supporting silicon bring-up and debug.
Role type
Senior IC DFT/ATPG Engineer (Mixed-Signal IP)
Builds
Production test patterns, scan architectures, and validation strategies for analog/mixed-signal IP
Domain
Semiconductor / Mixed-Signal IC Design
Required skills
Scan architecture design, ATPG modeling, fault simulation, gate-level netlist validation, zero-delay/SDF simulation, Python/Perl/Tcl scripting, silicon bring-up support
Preferred skills
Analog/mixed-signal DFT methodologies, advanced fault models (stuck-at, transition-delay, bridging), waveform debugging, yield learning, failure analysis
Technologies
ATPG tools, gate-level simulators, waveform debuggers, Python, Perl, Tcl
Responsibilities
Define and document scan architectures for analog and mixed-signal IP; Develop and maintain ATPG models for custom circuitry; Validate scan-stitched gate-level netlists; Analyze and improve test coverage across fault models; Perform zero-delay and SDF-annotated simulations; Own the lifecycle of production test patterns; Support silicon bring-up, yield learning, and post-silicon debug
Seniority
Senior, hands-on IC
