Senior Physical Design Engineer
Core
Delivering physical design of blocks/tiles for AMD next-generation chips to meet frequency, power, and other design requirements.
Role type
Senior IC physical design engineer (ASIC)
Builds
Next-generation semiconductor chips (processors)
Domain
Semiconductor / Hardware Design
Required skills
RTL to GDS2 flow implementation, floorplanning, power planning, synthesis, placement, CTS, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, EM/IR, formal equivalence, PNR tools (Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Calibre, Genus, Innovus), scripting for automation
Preferred skills
Automated synthesis and timing-driven place and route, clock and power gating techniques, scan stitching, design optimization for timing/power/area, IP integration, logic equivalence checks, familiarity with schematic/layout/circuit simulation tools
Technologies
Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
Responsibilities
Implement RTL to GDS2 flow, Handle floor-plan, physical implementation, power-plan, synthesis, placement, CTS, timing closure, routing, extraction, physical verification, crosstalk analysis, EM/IR, formal equivalence, Provide technical support to other teams
Seniority
Mid-level (3-5 years experience), hands-on IC
