RTL Design Manager
Core
Lead a small, high-performance engineering team to own the design and implementation of RTL blocks for cutting-edge SoC designs, ensuring first-pass silicon success.
Role type
Senior RTL Design Manager (Front-end Design/Integration)
Builds
Front-end RTL blocks and SoC integration for next-gen processors and AI technologies
Domain
Semiconductor / Digital IC Design
Required skills
RTL design and implementation, SoC level design integration, verification guidance, test and debug logic design, automation scripting (Perl/Python/Tcl), timing constraints and exceptions, LINT and CDC checks, UPF for power domains, Arm architecture protocols (APB, AXI, CHI), team leadership
Preferred skills
Design reuse strategies, timing analysis, design of experiment (DOE), self-starter mindset
Technologies
Arm, APB, AXI, CHI, Perl, Python, Tcl, LINT, CDC, UPF
Responsibilities
Lead a small, high-performance engineering team; Own the design and implementation of blocks to meet functional, timing, area and power requirements; Guide and review verification for these blocks; Design and implement logic functions that enable efficient test and debug; Implement automation to increase design team efficiency
Seniority
Senior, hands-on IC
