PD PNR Engineer
Core
End-to-end physical implementation and convergence of complex SoC/IP tiles, driving floorplanning, place-and-route, timing closure, and power/area optimization.
Role type
Senior IC physical design engineer (tile PnR)
Builds
Next-gen processors (CPU, GPU, NOC, AI/ML) and complex SoC/IP tiles
Domain
Semiconductor / VLSI / ASIC
Required skills
floorplanning, placement, CTS, routing, timing closure, ECO implementation, STA, scripting (Tcl/Python/Perl/Shell), debugging, PPA optimization
Preferred skills
advanced technology nodes (5nm/4nm/3nm), EMIR/CDC/RDC methodologies, Synopsys Fusion Compiler/ICC2/PrimeTime/RedHawk, AI-assisted PD flows, mentoring
Technologies
Synopsys Fusion Compiler, ICC2, PrimeTime, RedHawk, Tcl, Python, Perl, Shell
Responsibilities
Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff; Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization; Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets; Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration; Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges; Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency; Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing
Seniority
Senior, hands-on IC
