PD Leadership role
Core
Lead physical design implementation and timing closure for high-performance SOCs/ASICs from RTL to GDSII, ensuring first-pass silicon success across AI, graphics, and automotive domains.
Role type
Senior IC Physical Design Architect (RTL2GDSII)
Builds
High-performance SOCs/ASICs for AI Data Centres, Game Consoles, Discrete Graphics, Laptops, Telecom, and Automotive
Domain
Semiconductor / Physical Design / RTL2GDSII
Required skills
Physical design implementation, Timing closure, Power optimization, Signoff strategies, Synthesis, Constraints, PnR, Physical verification, IP integration, Foundry DRM collaboration, EDA tool expertise (Synopsys/Cadence), Scripting (Perl/TCL/Python), Project management (5-10 tape-outs)
Preferred skills
SOC/Block-level implementation, PPA optimization, Formal Equivalence, Low Power Checks, AI technologies in RTL2GDSII
Technologies
Fusion compiler, ICC2, Primetime, Redhawk, PTPX, Verilog, VHDL
Responsibilities
Lead RTL2GDSII implementation for multiple SOCs, mentor team members, drive methodology development, collaborate with cross-functional teams, define KPIs, represent company in industry forums
Seniority
Senior, hands-on IC with strategic leadership
