Senior Staff Pre Silicon Verification Engineer
Core
Architecting and developing simulation and formal-based verification environments for DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC) to ensure first-pass silicon success.
Role type
Senior Staff IC silicon verification engineer (memory controller, crypto, NoC)
Builds
Pre-silicon verification environments for high-performance memory controllers, crypto accelerators, and NoC blocks
Domain
Semiconductor / VLSI / Memory / High-speed interfaces
Required skills
UVM, System Verilog, formal verification, assertion-based verification, regression management, team leadership, verification strategy, testbench development, simulation environment architecture
Preferred skills
DDR/LPDDR/HBM protocol expertise, board skew and jitter modeling, gate-level simulation, power-aware verification, silicon debug, formal property checking tools (VC Formal, JasperGold, Questa Formal)
Technologies
Synopsys VCS, Cadence Xcelium, VC Formal, JasperGold, Questa Formal, UVM, System Verilog
Responsibilities
Lead verification of high-speed Crypto, NoC, and DRAM Memory controller designs; Architect and develop simulation/formal verification environments at IP and SoC-level; Lead and manage verification teams including planning, execution, tracking, and closure; Develop comprehensive verification plans and testbenches; Collaborate with design and architecture teams to define verification strategies; Mentor junior engineers
Seniority
Senior Staff, hands-on IC with team leadership
